May , 2006
TCAD Simulation of CompoundSemiconductor Electronic Devices
Olin Hartin, Ph.D.
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006.
Objective of Workshop
►This workshop will begin with a review of the fundamentals of TCAD simulation and available tools. DC and small signal AC simulation of devices will be discussed in detail. There will be a focus on calibration and the meaning of that calibration. The fundamentals of heterostructure simulation will be presented with examples.
Outline of Workshop
– Gate leakage Solutions in TCAD DC Simulation syntax Mixed mode
►Examples
Objective of TCAD simulation
►When TCAD is used to solve a problem the most critical step is to demonstrate the problem in TCAD
• If you can’t simulate the problem, it may be difficult to use TCAD to find the problem or simulate the solution
Objective of TCAD simulation
The objective of TCAD is to leverage prediction to solve problems that lead to better technologies
• Since prediction is the objective then it is important to understand the concept of prediction
Compact models are fit to a training data set, they can then predict the performance of a device ~within the range of the training data set
TCAD is calibrated to a dataset,
Outline of Workshop
►Vendor review
– Gate leakage Solutions in TCAD DC Simulation syntax Mixed mode
►Examples
TCAD Tools
►Major tool TCAD tool vendors
Sentaurus A typical simulation would have these elements
– S-Process (Floops) -> S-Edit (Devise)-> S-Device (Dessis)
Outline of Workshop
• Process simulation
– Gate leakage Solutions in TCAD DC Simulation syntax Mixed mode
►Examples
Process simulation
►What do these tools do?
• Process
As closely as is reasonable fabricate the device in simulation
– In Silicon simulation process is the challenge, in compound semiconductors the greater challenge is typically in the device simulation
Retain as many details as possible
– That makes it possible for you to use simulation to create spits on those process steps
The tools are designed mostly for silicon simulation so there are compromises
Process simulation
There are two potential objectives of process simulation
1. Investigate the process, and itsvariability using process simulation for development, (this is common in development
of Silicon devices, not so much in development of compound semiconductor devices)
2. Build a structure that accurately describes a device for device simulation, this is more common in compound semiconductors, this can be done in three ways
Process simulation
Outline of Workshop
• Process simulation
• Gridding
• Device simulation Heterostructure simulation Convergence Transport options Trap models Stress Quantum correction Material properties Special topics
– Gate leakage Solutions in TCAD DC Simulation syntax Mixed mode
►Examples
Creating a grid
►Edit
► Remember the device is only described in the simulator at the grid points More grid points are not always good
– The grid becomes stiffer
– The simulation gets a lot slower You want the smallest number of grid points that is sufficient to describe the solution Your grid will be mechanism dependent If there are surface traps -decrease the vertical grid spacing at the surface to describe
the trap depletion
Gridding problems
►There isn’t a fool proof analytical gridding algorithm for compound semiconductor devices that I am aware of
You may be able to run a simulation up to the point where convergence fails and then save the output
• Just remember, mistakes often show up as convergence problems
Gridding case study
count regions A courser grid isn’t as stiff, and generally converges better overall Solution cutbacks occur when convergence fails
Outline of Workshop
– Gate leakage Solutions in TCAD DC Simulation syntax Mixed mode
►Examples
charge
band discontinuities
►Poisson is then used to determine the potential due to charge
Heterostructure TCAD
Coupled equations are solved using a Newton’s method approach
– The more effects included, the more equations, the more memory and the more time required
Transport mechanisms, Poisson,
Quantum – solve multiple eqns DC AC
Device Simulation
Drift diffusion, or Hydrodynamic drive Schroedinger solver, or Density Gradients
Fixed or Hydrogenic
Solve { Poisson Coupled {Poisson Electron} Quasistationary (Goal { Name="gate" Voltage=2 }) { Coupled {Poisson Electron} } }
^{ Temperature }Hydrodynamic – solution based on Boltsman Mixed mode
transport considering energy of carriers
Outline of Workshop
– Gate leakage Solutions in TCAD DC Simulation syntax Mixed mode
►Examples
Convergence control
• Impatience is your enemy
< 1
− Digits
ε _{R }= 10
∆ x
<ε
+^{ε }^{A}x^{ε }R
Transport Options
Velocity models
• There are two choices
1. more complex, and harder to use
Velocity model
Velocity (cm/sec)
2.5 ^{.}10^{7 }
2 ^{.}10^{7 }
1.5 ^{.}10^{7 }
GaAs | |||
0 5 101520
kV/cm
►Must include energy dependent ^{2 }
1.5
relaxation times
EDRT (ps)
1
2
0.5
0
1.5
0 1000 2000 3000 4000 5000
Electron Temperature (K)
2
1
Increasing
1.5
InGaAs mole
0.5
Relaxation time (ps)
EDRT (ps)
fraction
1
0
0 0 1000 2000 3000 4000 5000
Electron Temperature (K)
Energy relaxation rate
►Energy relaxation rate
80
60
dW ⎛ T −T ⎞ _{A }_{)}
n 3 nL 3
= _{⎜}⎜ kn + kT_{n}R_{SRH }_{⎟}⎟λ_{n }+ E_{g }(G_{n }− R_{n}dt ^{2 }τ ^{2}
⎝ en ⎠ 40
w_{n }− w_{0}
R = ^{20 }
τ
0
Electron Temperature (K)
Energy relaxation rate (x1e10)
Energy vs Field
►GaAs, AlGaAs, and InGaAs
1 ^{.}10^{3 }1 ^{.}10^{4 }1 ^{.}10^{5 }1 ^{.}10^{6 }
►Trap types
based on changing bias conditions Acceptor and eNeutral traps
– Uncharged when unoccupied and carry a charge of one electron when occupied Donor and hNeutral traps
– Are uncharged when unoccupied and they carry the charge of one hole when fully occupied
►Traps can be defined with different distributions of charge, the most common is Gaussian, but table input is also interesting
_{−}(E−E_{0 })^{2 }2E
s
n = N_{0}e ^{2 }
►N_{0 }is the concentration, E_{0 }is the center of the trap energy distribution,and E_{s }is the sigma
Density Gradient Model
n
►γ is a fit factor
Quantization model
Outline of Workshop
– Gate leakage
Solutions in TCAD DC Simulation syntax Mixed mode
►Examples
Peak Electric Field
Peak Electric Field
This slide shows the calibration between simulated and measured 2 terminal breakdown current as a function of temperature from 25 to 150C The mechanisms are impact ionization and thermionic field emission
Tunneling and Impact Ionization
►This is an illustration of the proposed gate to drain breakdown mechanism. Here electrons tunnel in along the gate Electron Tunnelingdue to high reverse fields. Tunneling is
anticipated to occur for fields near 1e6
e
^{φ}_{Μ}
V/cm[Robbins, 1988 #3].
Gate
►Impact ionization occurs in AlGaAs and
InGaAs material below resulting in holes that escape to the gate, populate surface states altering channel depletion and degrading performance, and escape to the substrate.
E
^{E}c
h
►Neither mechanism alone accounts for the current observed in measured data
^{E}v because the tunneling mechanism feeds carriers to the avalanche mechanism
PHEMT Structure
Impact Ionization Parameters
►AlGaAs in 10% molefraction
1 ^{.}10^{6 }
increments
►InGaAs 20% molefraction
1 ^{.}10^{3 }100
10 1
0.1
1/Electric Field (cm/V)
Impact ionization Generation
alpha
Outline of Workshop
– Gate leakage
Solutions in TCAD DC Simulation syntax Mixed mode
►Examples
How does it work?
Poisson : ∇⋅ε∇φ= −q(p − n + N − N )−ρ
D A trap
dnContinuity : ∇⋅ J = qR + q
n net
dt Drift Diffusion : J =−nqµΦ
n nn
td 3
Hydrodynamic : J = qµ(n∇E + kT ∇n + f kn∇T + nkT ∇ ln m )
nncn nn 2 nn
γ h^{2}∇^{2 }n
Density Gradients : Λ= ^{n }6m_{n }n
►LU decomposition of the Jacobian is typically done
J (x )(x − x ) =−F(x )
Fn n+1 nn
x = x − J (x )^{−1 }F(x )
n+1 nFn n
Outline of Workshop
– Gate leakage Solutions in TCAD DC Simulation syntax Mixed mode
►Examples
Electrode {
DC Solution
{ Name="Source" Voltage=0 Resistor=417} { Name="Drain" Voltage=0 Resistor=417} { Name="Gate" Voltage=0 WorkFunction=5.2 Resistor=300 }
{ Name="substrate" Voltage=0 schottky barrier=0.7 } }File {
Grid = "input/ggofet_mdr"
Doping = "input/ggofet_mdr"
Current = "d_ox/plot"
Output = "d_ox/log"
Plot = "d_ThuFeb15122658200719/dat"
Parameter = "../../common_files/specific.par" }Plot {
EtrappedCharge
Egapstatesrecombination
htrappedcharge
hgapstatesrecombination
Potential Electricfield
eDensity hDensity
eCurrent/Vector hCurrent/Vector
TotalCurrent/Vector
SRH Auger
eMobility hMobility
eQuasiFermi hQuasiFermi
eGradQuasiFermi hGradQuasiFermi
eEparallel hEparallel
eMobility hMobility
eVelocity hVelocity
DonorConcentration AcceptorcCncentration
Doping SpaceCharge
ConductionBand ValenceBand
BandGap Affinity
xMoleFraction
Note that electrodes are defined with resistor values that are scaled by the areafactor here it is 1000, so the actual source resistance implied Is 0.417
DC Solution
Math { CNormPrint Extrapolate Digits = 5 NotDamped=1000 Iterations=25 NewDiscretization ConstRefPot ElementEdgeCurrent Derivatives RelErrcontrol NUpperLimit=1e40 RhsFactor=1e20 CdensityMin=1e-10 ErrRef(electron)=1e8 ErrRef(hole) =1e8 DirectCurrent
}
Physics { Fermi eQuantumPotential HeteroInterfaces AreaFactor = 1000 Hydro(etemperature) Recombination( SRH Auger )
Describe the Physics
Here a mole fraction of 20% is given
InGaAs has a 30% mole fraction but as it is strictlydefined using the software thiswould be 70% Indium (we haveour own internal materials file which has the oppositespecification)
DC Solution
Physics ( Material = "AlGaAs" ) {MoleFraction(
XFraction=0.2 ) EffectiveIntrinsicDensity( Nobandgapnarrowing ) Traps(
(Acceptor Conc=1e14 EnergyMid=0.62 fromCondBand eXsection=1e-14 hXsection=2e-13) (Donor Conc=1e15 EnergyMid=0.61 fromValBand eXsection=2e-18 hXsection=2e-18)
) Mobility (
eHighFieldSaturation(CarrierTempDrive)hHighFieldSaturation(GradQuasiFermi) )}
Physics ( Material = "InGaAs" ) {EffectiveIntrinsicDensity( Nobandgapnarrowing )MoleFraction(
XFraction=0.3 ) Mobility (
eHighFieldSaturation(CarrierTempDrive)hHighFieldSaturation(GradQuasiFermi)
)}Physics ( MaterialInterface = "Oxide/GaAs" ) {
Traps(conc=-1e9 fixedcharge) }
Solve { DC Solution
Coupled(Iterations=50) { Poisson } Coupled(Iterations=50) { Poisson Electron Hole } Coupled(Iterations=50) { Poisson eQuantumPotential } Coupled(Iterations=50) { Poisson Electron Hole eTemperature eQuantumPotential }
Quasistationary ( InitialStep=2e-2 Minstep=1e-8 MaxStep=0.20 Increment=1.4 Goal { Name="Gate" Voltage=2 }
) { Coupled { Poisson Electron Hole eTemperature eQuantumPotential } currentplot ( time=(range=(0 1) intervals=40 ) )
}
Quasistationary ( InitialStep=5e-2 Minstep=1e-8 MaxStep=0.20 Increment=1.4 Goal { Name="Drain" Voltage=2.0 }
) { Coupled { Poisson Electron Hole eTemperature eQuantumPotential } currentplot ( time=(range=(0 1) intervals=5 ) )
}
Quasistationary ( InitialStep=5e-2 Minstep=1e-8 MaxStep=0.20 Increment=1.4 Goal { Name="Drain" Voltage=2.0 }
) { Coupled { Poisson Electron Hole eTemperature eQuantumPotential } currentplot ( time=(range=(0 1) intervals=5 ) )
} }
To get initial solution use coupled solutions with additional equations
Current plot gives solutions at predefined points
Sweep the gate, then the drain, then sweep the gate back to get cut off
– Gate leakage Solutions in TCAD DC Simulation syntax Mixed mode
Outline of Workshop
Mixed Mode Simulation
Device FET1 { | |
---|---|
Electrode { | |
{ name=“source” voltage=0 Res=200 } | |
{ name=“drain” voltage=0 Res=200 } | |
{ name=“gate” voltage=0 Res=200 } | |
{ name=“sub” voltage=0 Res=200 } | |
} | |
Physics | { |
… | |
} | |
Plot | { |
… | |
} | |
Math | { |
… | |
} | |
File | { |
… | |
} | |
System { |
FET1 DEV ( drain=dt gate=gt source=st sub=st) v v_g(gt 0) {type=“dc” dc=0} v v_d(dt 0) {type=“dc” dc=0} v v_s(st 0) {type=“dc” dc=0}
}
Quasistationary (
InitialStep=1e-2 Minstep=1e-7 MaxStep=0.2 Increment=1.4
Goal { Parameter=v_g.dc Voltage= 2.0 } ) { Coupled { Poisson Electron Hole eTemperature eQuantumPotential } }
Quasistationary (
InitialStep=1e-2 Minstep=1e-7 MaxStep=0.2 Increment=1.4
Goal { Parameter=v_d.dc Voltage= 2 } ) { Coupled { Poisson Electron Hole eTemperature eQuantumPotential } }
Quasistationary (
InitialStep=1e-2 Minstep=1e-7 MaxStep=0.2 Increment=1.4
Goal { Parameter=v_g.dc Voltage= 0 }) { currentplot (time=(range=(0 1) intervals=40 ) )
ACCoupled ( StartFrequency=0.5e9 EndFrequency=20.0e9 NumberOfPoints=39 Linear
ACCompute (time=(range=(0 1) intervals=40 ))
)
{ Poisson Electron Hole eTemperature eQuantumPotential }
}}
– Gate leakage Solutions in TCAD DC Simulation syntax Mixed mode
Outline of Workshop
Calibration What does it mean?
First: Determine every parameter possible from measured data and from the literature
►For the parameter values that cannot be determined determine the reasonable range
– As a result the model is only valid in the range of the measured data it was fit to Physical device simulation uses a physical description of the device and mechanisms at grid points
Calibration to measured data FET Procedure
Calibration to measured data HBT Procedure
– Gate leakage Solutions in TCAD DC Simulation syntax Mixed mode
Outline of Workshop
• Objectives of simulation
Examples: Objectives of TCAD
recombination parameters including band gap narrowing Surface effects are important near contacts
– Gate leakage Solutions in TCAD DC Simulation syntax Mixed mode
Outline of Workshop
• Objectives of simulation
Example HBT
• and lateral grid spacing is typically decreased around lateral device discontinuities such as contacts and etches
emitter
– Gate leakage Solutions in TCAD DC Simulation syntax Mixed mode
Outline of Workshop
Example GaAs MOSFET
►The device as a Gadolinium GaAs Oxide layer under the gate, it employs delta doping and a InGaAs Channel
GaAs Oxide (κ=20) |
---|
2 nm undoped Al45GaAs |
2 nm undoped GaAs |
10 nm undoped In30GaAs |
2 nm undoped GaAs |
3 nm undoped Al30GaAs |
65 nm undoped Al30GaAs |
0.2 µm undoped GaAs |
GaAs Substrate |
Example GaAs MOSFET
• Threshold of ~0.25 volts is achieved
Simulated and Meausred: Id/Vg Characteristics
Drain Current vs Gate Voltage
Gate Voltage (V)
►Log(Id)/Vg characteristic shows
log Drain Current vs Drain Voltage
1000
the sub-threshold swing (s) of 100 [mv/dec]
100 | |||||
10 | |||||
1 | |||||
0.1 0. | 00 0.50 | 1.00 | 1.50 | 2.00 | |
0.01 | |||||
0.001 | ID (mA/mm) | ||||
0.0001 | sim Id/Vd | ||||
Gate Voltage (V)
Simulated vs Measured Id/Vd Characteristic
►Set saturation velocity to 1.3e7 cm/sec
• This is not completely
Drain Current vs Drain Voltage
physical _{450 }
►Set the effective contact
resistance to achieve the
same on resistance
observed in the device
• This usually has to do with
access resistance which is
Drain Current (mA/mm)
400 350
300
250 200
150
100
50
0
not typically accurately
-50
measured
• In this case the access resistance used in the simulation was ~.6 ohm mm
Comparison to measured data
Check R= 2*R+ 0.85*2*R_{sh }+ L*R_{ch }≈ 2.25 Ω
onc g
par | Simulation | Measured | Error | Units |
Vth | 0.254 | 0.25-0.27 | on | volts |
Ron | 2.23 | 2.25 | 0.9% | ohm mm |
S | 100 | 106 | 6% | mv/dec |
Idss | 427 | 435-421 | >2% | mA |
Rsh | 461 | 449 | 2.6% | mA |
Rc | 0.617 | 0.417 | 47% | ohm mm |
– Gate leakage Solutions in TCAD DC Simulation syntax Mixed mode
Outline of Workshop
– Calibration
AC
– Small signal analysis
AC characteristics
_{⎡}R_ _{g }+ L_ _{g}⋅ω⋅1i +(R_ _{s }+ L_ _{s}⋅ω⋅1i)(R_ _{s }+ L_ _{s}⋅ω⋅1i)_{⎤ }⎢⎥
_{⎣}(R_ _{s }+ L_ _{s}⋅ω⋅1i) R_ _{d }+ L_ _{d}⋅ω⋅1i +(R_ _{s }+ L_ _{s}⋅ω⋅1i)_{⎦ }
S parameters
►S parameters that result, both intrinsic and extrinsic s
G+iA Z
^{S}intrinisic
parameters are shown
_{90 }^{Z+Z}e ^{S}extrinsic
270
GridZ s11
Small Signal Gain
30
Add gate resistance
25
Gate inductance Load inductance _{20 }
Impact of these parasitics _{15 }is, Fmax is decreased from from ~200 to 20 GHz _{10 }
Source inductance … _{5 }
0
S | 21 | /S | 1 | 2 | |||||||||||||||||||||||
2 | 3 | .5 | |||||||||||||||||||||||||
Ma | xi | m | u | m | |||||||||||||||||||||||
S | ta | b | le | ||||||||||||||||||||||||
Ga | in | ||||||||||||||||||||||||||
TC | AD | ||||||||||||||||||||||||||
Ma | xi | mu | m | ||||||||||||||||||||||||
Av | ail | ab | le | ||||||||||||||||||||||||
Ga | in | ||||||||||||||||||||||||||
0 |
0.1 1 10 100 Frequency (GHz)
Maximum Practical Gain (dB)
You must have a good handle on parasitics to get the right answer
►Impact of Source Inductance is to significantly reduce the corner frequency
30
which results in lower gain at
high frequency
In some cases the source inductance is not well known but can be set to achieve the
gain observed
Maximum Practical Gain (dB)
25
20
15
10
5
Frequency (GHz)
30
also impact the gain curve and
the location of the corner
frequency
Maximum Practical Gain (dB)
20
15 10 5
0
Frequency (GHz)
– Gate leakage Solutions in TCAD DC Simulation syntax Mixed mode
Outline of Workshop
– Calibration
AC
– Small signal analysis
PHEMT Switch Evaluation of Harmonics
PHEMT TCAD Calibration
►SPDT Switch implemented ^{to Measured Data }with PHEMT multi gate switches
DC I/V
S param
Single Pole Double Throw Switch Simulation
System {*----------------------------------------------------------------------*
HEMT phemt (Source=s Drain=d Gate1=g1 Gate2=g2 Gate3=g3 )Plot "switch" (time() v(s) v(d) v(n2) i(s d) i(s n2) )
Vsource_pset vs ( vs 0 ) { sine =(0 1.25892541179417 1e9 0 0) } Resistor_pset Rin ( vs s ) { resistance = 50 } Resistor_pset RD ( s d ) { resistance = 16000 } Vsource_psetvc( vc0 ) { dc = 0 }
Resistor_pset Ron (s n2) { resistance = 2.35 } Resistor_pset RL_ (n2 0) { resistance = 50 } Resistor_pset RL (d 0) { resistance = 50 }
Resistor_pset RG1 (g1 vc) { resistance = 16000 } Resistor_pset RG2 (g2 vc) { resistance = 16000 } Resistor_pset RG3 (g3 vc) { resistance = 16000 }
*
* Switch circuit *----------------------------------------------------------------------* }
More complex mixed mode simulations can be done including ones with multiple active devices and ideal passive components, here a single pole double throw circuit is described In this case we are doing a single pole double throw simulation with a switch composed of two devices
On device | |
---|---|
Off device | looks like |
Looks is modeled | a resistor |
Switch Simulation
Solve { *----------------------------------------------------------------------* *--Computing initial guess:
NewCurrentFile=off
circuit Coupled( Iterations=100 ){ Poisson Contact Circuit } Coupled { Poisson Contact Circuit Electron Hole eTemperature }
Quasistationary ( InitialStep=1e-2 Increment=1.2 Minstep=1e-8 MaxStep=0.1 Goal{ parameter=vc.dc Value=-3 } )
{ Coupled { Poisson Contact Circuit Electron Hole eTemperature } }
NewCurrentFile=off_
Transient ( InitialTime=0 FinalTime=2e-9 InitialStep=3.90625e-12 MaxStep=3.90625e-12 MinStep=1e-17 Increment=1.2
)
{ Coupled { Poisson Contact Circuit Electron Hole eTemperature } CurrentPlot (
Time = ( Range=( 0.0 2e-9 ) intervals=512 ) ) } plot
Transient Simulations
– Gate leakage Solutions in TCAD DC Simulation syntax Mixed mode
Outline of Workshop
– Calibration
AC
– Small signal analysis
Large Signal
► There are three ways to do large signal simulations using TCAD
Not operable for practical problems, long simulations, not well integrated with designs
3. Extract a model based on TCAD Limits to what the model is capable, well integrated with designer
75
20
Pout
20
60.3 62.3
50
Pout (dBm)
Gain (dB)
PAE (%)
10
10
15.84 16.76
22.26 22.54
58 59.2 60.4 61.6 62.8 64
25
Gain
PAE
PAE (%)
a
0
-30 -20
-10 0 1020
15 15.6 16.2 16.8 17.4 18
22 22.2 22.4 22.6 22.8 23
Low Power Gain (dB 0
0
Pout (dBm)
-10
-30 -20 -10 0 10 20
-30 -20 -10 0 10 20
Pin (dBm)
Pin (dBm)
Pin (dBm)
In Review
►Heterostructure process and device simulation can be done using basic methods. Key mechanisms necessary for FETs and Bipolars are available in commercial vendor packages. Methods exist that make it possible to integrate known material data and calibration to measured data. These methods enable TCAD simulations for DC, small signal AC, and large signal prediction.
References
Hartin, O., et al. (2001). Compound Semiconductor Physical Device Simulation for Technology Development at Motorola. GaAs IC Symposium 23^{rd }Annual Technical Digest:163-165 Li, P. H., et al. (2002). “An updated temperature-dependent breakdown coupling model including both impact ionization and tunneling mechanisms for AlGaAs/InGaAs HEMTs.” IEEE Transactions on Electron Devices 49(9): 1675-1678. Quay, R. (2001). Analysis and Simulation of High Electron Mobility Transistors. Electrical Engineering. Freiburg, Technischen Universität Wien Fakultät für Elektrotechnik und Informationstechnik. Klimeck, G., R. Lake, et al. (1996). Nemo: A General Purpose Quantum Device Simulator. Texas Instruments Research Colloquium, Dallas, TX. Sentaraus Manual version Y-2006.06 Silvaco Atlas Manual 5^{th }Edition, 1997 Kalna, K., et al. (2007). “Monte Carlo Simulations of High-Performance Implant Free In0.3Ga0.7As Nano-MOSFETs for Low-Power CMOS Applications.” IEEE Transactions on Nanotechnology 6(1). Rajagopalan, et al. (2007). “1-ìm Enhancement Mode GaAs N-Channel MOSFETs With Transconductance Exceeding 250 mS/mm.” IEEE ELECTRON DEVICE LETTERS 28(2). Adachi, S., Ed. (1993). Properties of Aluminum Gallium Arsenide. EMIS Data Reviews Series. London, INSPEC, the Institution of Electrical Engineers. Adachi, S. (1994). GaAs and Related Materials: Bulk Semiconducting and Superlattice properties. London, World Scientific. Vendelin, G. D., A. M. Pavio, et al. (1990). Microwave Circuit Design. New York. Lundstrom, M. (1990). Fundamentals of Carrier Transport. Reading, Ma., Addison Wesley Publishing Co. Vogl, P. (1983). “A Semi-Empirical Tight-Binding Theory of the Electronic Structure of Semiconductors.” Journal of the Physical Chemistry of Solids 44(5): 365-378. Wolfe, C. M., J. Nick Holonyak, et al. (1989). Physical Properties of Semiconductors. Engelwood Cliffs, New Jersey, Prentice hall. Blakey, P. A., Ed. (2001). Technology Computer Aided Design. The RF Microwave Handbook. London, CRC Press.